2024-03-29T08:47:38Z
https://u-ryukyu.repo.nii.ac.jp/oai
oai:u-ryukyu.repo.nii.ac.jp:02005166
2022-10-31T02:31:18Z
1642837622505:1642837855274:1642837875288
1642838403551:1642838406845
4値VTゲート回路網の合成
Synthesis of Quaternary VT-gate Networks
比嘉, 広和
瑞慶覧, 長定
島袋, 勝彦
Higa, Hirokazu
Zukeran, Chotei
Shimabukuro, Katsuhiko
open access
VT-gate
Implicant
Recently one of the most important problems is the pin limitations in the integrated circuits. Multiplevalued logic has attracted for solution of the problem. because for the same amount of information transfer, the total number of pins required in the multiple-valued integrated circuit chip is much less than that of an binary integrated. In this paper, we discuss synthesizing quaternary VT-gate networks. (VT-gate has variable threshold) An implicant in the function plays important role when synthesizing VT-gate networks. Because we can reduce the number of VT-gates in the networks by utilizing implicant. We apply a candidate for implicant in eval function and show good result was obtained.
紀要論文
琉球大学工学部
1999-03
jpn
departmental bulletin paper
VoR
http://hdl.handle.net/20.500.12000/14148
http://hdl.handle.net/20.500.12000/14148
https://u-ryukyu.repo.nii.ac.jp/records/2005166
0389-102X
AN0025048X
琉球大学工学部紀要
57
59
63
https://u-ryukyu.repo.nii.ac.jp/record/2005166/files/No57p059.pdf