2024-03-29T10:43:49Z
https://u-ryukyu.repo.nii.ac.jp/oai
oai:u-ryukyu.repo.nii.ac.jp:02001559
2022-10-31T00:50:49Z
1642837622505:1642837855274:1642837876648
1642838403551:1642838406845
琉球大学HDLデザイン・コンテスト2000結果報告
University of the Ryukyus HDL Design Contest 2000 Summary
和田, 知久
翁長, 健治
宮城, 隼夫
吉田, たけお
尾知, 博
Wada, Tomohisa
Onaga, Kenji
Miyagi, Hayao
Yoshida, Takeo
Ochi, Hiroshi
HDL
VHDL
Verilog HDL
Design Contest
Universities nationwide gathered in Okinawa, Japan, on March 3rd to participate in University of the Ryukyus HDL Design Contest 2000 hosted by the University of the Ryukyus' Department of Information Engineering. Of the 15 applicants, ten finalists were chosen for the contest with their original designs on Galois Field matrix multiplier for Redundant Array of Inexpensive Disks System. A proud and triumphant team of juniors from the Department of Information Engineering at the University of the Ryukyus (the team "Turtlenecks") was awarded first prize, defeating the more experienced Masters students from other universities.
紀要論文
http://purl.org/coar/resource_type/c_6501
琉球大学工学部
2000-09
VoR
http://hdl.handle.net/20.500.12000/1431
0389-102X
AN0025048X
琉球大学工学部紀要
60
94
89
jpn
open access