{"_buckets": {"deposit": "bd0e3c07-5cc2-4fd9-9d9b-953ef80dc808"}, "_deposit": {"id": "2005166", "owners": [1], "pid": {"revision_id": 0, "type": "depid", "value": "2005166"}, "status": "published"}, "_oai": {"id": "oai:u-ryukyu.repo.nii.ac.jp:02005166", "sets": ["1642837875288", "1642838406845"]}, "author_link": [], "item_1617186331708": {"attribute_name": "Title", "attribute_value_mlt": [{"subitem_1551255647225": "4値VTゲート回路網の合成", "subitem_1551255648112": "ja"}, {"subitem_1551255647225": "Synthesis of Quaternary VT-gate Networks", "subitem_1551255648112": "en"}]}, "item_1617186419668": {"attribute_name": "Creator", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "比嘉, 広和", "creatorNameLang": "ja"}]}, {"creatorNames": [{"creatorName": "瑞慶覧, 長定", "creatorNameLang": "ja"}]}, {"creatorNames": [{"creatorName": "島袋, 勝彦", "creatorNameLang": "ja"}]}, {"creatorNames": [{"creatorName": "Higa, Hirokazu", "creatorNameLang": "en"}]}, {"creatorNames": [{"creatorName": "Zukeran, Chotei", "creatorNameLang": "en"}]}, {"creatorNames": [{"creatorName": "Shimabukuro, Katsuhiko", "creatorNameLang": "en"}]}]}, "item_1617186476635": {"attribute_name": "Access Rights", "attribute_value_mlt": [{"subitem_1522299639480": "open access", "subitem_1600958577026": "http://purl.org/coar/access_right/c_abf2"}]}, "item_1617186609386": {"attribute_name": "Subject", "attribute_value_mlt": [{"subitem_1522299896455": "en", "subitem_1522300014469": "Other", "subitem_1523261968819": "VT-gate"}, {"subitem_1522299896455": "en", "subitem_1522300014469": "Other", "subitem_1523261968819": "Implicant"}]}, "item_1617186626617": {"attribute_name": "Description", "attribute_value_mlt": [{"subitem_description": "Recently one of the most important problems is the pin limitations in the integrated circuits. Multiplevalued logic has attracted for solution of the problem. because for the same amount of information transfer, the total number of pins required in the multiple-valued integrated circuit chip is much less than that of an binary integrated. In this paper, we discuss synthesizing quaternary VT-gate networks. (VT-gate has variable threshold) An implicant in the function plays important role when synthesizing VT-gate networks. Because we can reduce the number of VT-gates in the networks by utilizing implicant. We apply a candidate for implicant in eval function and show good result was obtained.", "subitem_description_type": "Other"}, {"subitem_description": "紀要論文", "subitem_description_type": "Other"}]}, "item_1617186643794": {"attribute_name": "Publisher", "attribute_value_mlt": [{"subitem_1522300295150": "ja", "subitem_1522300316516": "琉球大学工学部"}]}, "item_1617186702042": {"attribute_name": "Language", "attribute_value_mlt": [{"subitem_1551255818386": "jpn"}]}, "item_1617186783814": {"attribute_name": "Identifier", "attribute_value_mlt": [{"subitem_identifier_type": "HDL", "subitem_identifier_uri": "http://hdl.handle.net/20.500.12000/14148"}]}, "item_1617186920753": {"attribute_name": "Source Identifier", "attribute_value_mlt": [{"subitem_1522646500366": "ISSN", "subitem_1522646572813": "0389-102X"}, {"subitem_1522646500366": "NCID", "subitem_1522646572813": "AN0025048X"}]}, "item_1617186941041": {"attribute_name": "Source Title", "attribute_value_mlt": [{"subitem_1522650068558": "ja", "subitem_1522650091861": "琉球大学工学部紀要"}]}, "item_1617187056579": {"attribute_name": "Bibliographic Information", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "1999-03", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "57", "bibliographicPageEnd": "63", "bibliographicPageStart": "59"}]}, "item_1617258105262": {"attribute_name": "Resource Type", "attribute_value_mlt": [{"resourcetype": "departmental bulletin paper", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_1617265215918": {"attribute_name": "Version Type", "attribute_value_mlt": [{"subitem_1522305645492": "VoR", "subitem_1600292170262": "http://purl.org/coar/version/c_970fb48d4fbd8a85"}]}, "item_1617605131499": {"attribute_name": "File", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_access", "download_preview_message": "", "file_order": 0, "filename": "No57p059.pdf", "future_date_message": "", "is_thumbnail": false, "mimetype": "", "size": 0, "url": {"objectType": "fulltext", "url": "https://u-ryukyu.repo.nii.ac.jp/record/2005166/files/No57p059.pdf"}, "version_id": "e81b02a4-1366-4507-ba58-7b0e6a00a603"}]}, "item_title": "4値VTゲート回路網の合成", "item_type_id": "15", "owner": "1", "path": ["1642837875288", "1642838406845"], "permalink_uri": "http://hdl.handle.net/20.500.12000/14148", "pubdate": {"attribute_name": "PubDate", "attribute_value": "2009-12-18"}, "publish_date": "2009-12-18", "publish_status": "0", "recid": "2005166", "relation": {}, "relation_version_is_last": true, "title": ["4値VTゲート回路網の合成"], "weko_shared_id": -1}